About Me
Carlos Marquez obtained his P.h.D in Electronics from the University of Granada in 2017. The M.S. degrees in Telecommunication Engineering and M.S. in Electrical Engineering, in 2012 and 2014, respectively from University of Granada, Granada, Spain. His research interests include the electrical characterization of semiconductor devices, MOSFET reliability, one-transistor dynamic-random-access-memory cells (1T-DRAM) and novel III-V and two dimensional (2D) materials for electronic applications. Particularly, his PhD research has involved the study of MOSFET degradation mechanisms such as bias instability (BI), random telegraph noise (RTN), impact ionization (II), low-frequency noise and their implications on VLSI design. He also participates in the fabrication, processing and characterization of novel 2D materials such as graphene or TMDs.
In 2019 he received a postdoctoral mobility fellowship to work at Tyndall National Institute, Cork, Ireland. Also he was granted with a `Juan de la Cierva Formación` postdoctoral grant (Spanish Science Minister) to be developed on GaN devices at Madrid Polytechnic University (Spain) during 2020. In 2020 he received a Marie Curie Global Fellowship under the project titled TRAPS-2D to be developed between National Chiao Tung University (Taiwan) and University of Granada (Spain) in 2021 and 2022.
Dr. Carlos Marquez is author or co-author of 20 peer-reviewed international journal articles, 4 book chapters, one patent application and 11 conference proceedings including ESSDERC, Graphene Canada and international IEEE SOI conference. He owns a best paper award in EuroSOI-ULIS 2018 conference. He has collaborated in 8 research projects, European two of them. In 2016 and 2018, he obtained two mobility fellowships at Tyndall National Institute-University College Cork, Ireland for 3 and 5 months, respectively. He worked there on the material deposition and characterization of two dimensional materials thanks to Ascent European Nanoelectronics Network and Jose Castillejo mobility programme. Additionally, in 2016, he was attendant at international Graphene Study course and the European School On Nanosciences and Nanotechnologies (ESONN), where he received trainings in the field of Nanosciences and Nanotechnologies specially focused on semiconductor fabrication and electrical characterization.
In academia, he holds the Assistant Professor accreditation by ANECA with teaching experience in analog/mixed-signal electronics.
He holds hand-on experience dealing with semiconductor devices fabrication, lithography and metallization processes and extended electrical characterization.
Journal Articles
- Investigating the transient response of Schottky barrier back-gated MoS2 transistors (2020), 2D Materials, 7, 025040
- Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm (2019), Nature Electronics, 2, 1-8
- Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell (2019), IEEE Electron Device Letters, 40, 1084–1087
- Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells (2019), Solid-State Electronics, 159, 12-18
- Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell (2019)
- 3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs (2019), IEEE Transactions on Electron Devices, 66, 2513-2519
- Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power (2019), IEEE Access, 7, 40279-40284
- On the Low-Frequency Noise Characterization of Z2-FET Devices (2019), IEEE Access, 7, 42551-42556
Conferences
- Investigating the transient response of Schottky barrier back-gated MoS2 transistors (2020), 2D Materials, 7, 2
- Temperature and Gate Leakage Influence on the Z2-FET Memory Operation,ESSDERC, Krakov, Sept 2019
- Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm (2019), Nature Electronics, 1-8
- Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells (2019)
- Multi-Subband Ensemble Monte Carlo Simulator for Nanodevices in the End of the Roadmap (2019)
- Capacitorless memory devices using virtual junctions (2019)
- Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell (2019)
- 3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs, IEEE Transactions on Electron Devices 66 (6), 2513-2519
Book Chapters
- Investigating the transient response of Schottky barrier back-gated MoS2 transistors (2020), 2D Materials, 7, 025040
- Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm (2019), Nature Electronics, 2, 1-8
- Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell (2019), IEEE Electron Device Letters, 40, 1084–1087
- Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells (2019), Solid-State Electronics, 159, 12-18
TRAPS-2D
Teaching
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