Javier Díaz

Latest

• Hierarchical architecture for motion and depth estimations based on color cues
• On-chip semidense representation map for dense visual features driven by attention processes
• Real-time visual saliency architecture for FPGA with top-down attention modulation
• Bottom-up visual attention model based on FPGA
• A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation
• Massive parallel-hardware architecture for multiscale stereo, optical flow and image-structure computation
• Parallel architecture for hierarchical optical flow estimation based on FPGA
• Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs
• Real-time architecture for a robust multi-scale stereo engine on FPGA
• Vector disparity sensor with vergence control for active vision systems