Source Themes

Real-time visual saliency architecture for FPGA with top-down attention modulation

Biological vision uses attention to reduce the visual bandwidth simplifying the higher-level processing. This paper presents a model and its hardware real-time architecture in a field programmable gate array (FPGA) to be integrated in a robotic …

Bio-inspired Motion Estimation with Event-Driven Sensors

This paper presents a method for image motion estimation for event-based sensors. Accurate and fast image flow estimation still challenges Computer Vision. A new paradigm based on asynchronous event-based data provides an interesting alternative and …

Bottom-up visual attention model based on FPGA

We present a model and a hardware architecture for the computation of bottom-up inherent visual attention for FPGA. The bottom-up inherent attention is generated including local energy, local orientation maps, and red-green and blue-yellow color …

Contour motion estimation for address-event data

Current motion estimation methods use very sophisticated techniques that require high computational complexity, with low time performance, and large resources. The current framework is considered exhausted. DVSs (Dynamic Visual Sensors) efficiently …

A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation

This paper presents a novel hardware-friendly motion estimation for real-time applications such as robotics or autonomous navigation. Our approach is based on the well-known Lucas & Kanade local algorithm, whose main problem is the unreliability of …

Massive parallel-hardware architecture for multiscale stereo, optical flow and image-structure computation

Low-level vision tasks pose an outstanding challenge in terms of computational effort, pixel-wise operations require high-performance architectures to achieve real-time processing. Nowadays, diverse technologies permit a high level of parallelism and …

Parallel architecture for hierarchical optical flow estimation based on FPGA

In this work, we present a real-time implementation of a stereo algorithm on field-programmable gate array (FPGA). The approach is a phase-based model that allows computation with sub-pixel accuracy. The algorithm uses a robust multi-scale and …

Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

This paper presents an architecture for the extraction of visual primitives on chip, energy, orientation, disparity, and optical flow. This cost-optimized architecture processes in real time high-resolution images for real-life applications. In fact, …

Real-time architecture for a robust multi-scale stereo engine on FPGA

In this work, we present a real-time implementation of a stereo algorithm on field-programmable gate array (FPGA). The approach is a phase-based model that allows computation with sub-pixel accuracy. The algorithm uses a robust multi-scale and …

Vector disparity sensor with vergence control for active vision systems

This paper presents an architecture for computing vector disparity for active vision systems as used on robotics applications. The control of the vergence angle of a binocular system allows us to efficiently explore dynamic environments, but requires …